【摘要】 针对卫星轻小型化的应用需求和现有1553B总线接口设计存在缺陷的问题,提出一种面向航天器综合电子的1553B总线协议ASIC芯片设计方案,并介绍了自主研发的1553B协议IP核设计.1553B IP核采用自顶向下的设计方法,使用Verilog硬件设计语言进行编程,实现了1553B总线中的总线控制器BC和远程终端RT功能.分别从1553B IP核总体框架、BC/RT共享模块、BC功能模块和RT功能模块详细介绍了IP核的设计.1553B IP核设计完成模块仿真验证、ASIC芯片系统仿真验证和FPGA验证,通过DDC的1553B板卡对设计进行验证,误码率小于10^-9.实验结果表明,本IP核设计具有可靠性高、可移植性强、资源占用少、实时性好的特点.更多还原

【Abstract】 It is a problem to miniaturize space avionics when we use traditional 1553B bus interface chips.To solve this problem,design of an ASIC chip for spacecraft integrated avionics is proposed.The design of a 1553B IP core with independent intellectual property in this chip is described in detail.The 1553B IP core includes the bus controller module,the remote terminal module,the Manchester decode and encode module,the shared RAM,the RAM arbitration module,the AXI bus slave interface module,the channel select module and the timer module.Each module is introduced.The top-down designing method is used and the program is described by Verilog hardware description language.The 1553B IP core design is tested and verified by the functional simulation,the ASIC system simulation and FPGA test.DDC’s 1553B test board is used to test the IP core.The test results indicate that the 1553B IP core design is reasonable.The design of 1553B IP core has good performance in reliability,portability,real-time and less resource occupancy.更多还原