节点文献
一种用于APFC的模拟乘法器设计
A analog multiplier for APFC
【摘要】 在有源功率因数校正技术(APFC)中,通过对乘法器的输出与电感电流的峰值比较,控制功率开关管的开启与关断,使输入电流峰值包络跟随输入电压,功率因数理论上为单位值。而提高乘法器的线性度,减小非线性误差成为研究模拟乘法器的一个重要方向。本文提出的模拟乘法器采用有源衰减器显著的增大了输入信号电压范围,更重要的是在有源衰减电路中引入负反馈有效的减小了乘法器的非线性误差。基于CSMC 0.5um BCD工艺,采用Hspice进行仿真验证,在电源电压5V条件下,乘法器的一输入端的输入范围为0~2V,非线性误差小于0.6%,另一输入端的输入范围为1~4V,非线性误差小于0.3%。总谐波失真小于1.8%。
【Abstract】 In active power factor correction technology(APFC),through to compare the peak inductor current and the multiplier output to control power switch on and off, so that the input current peak envelope follows the input voltage, power factor theory Unit values. And improve the linearity of the multiplier, reducing the nonlinear error has become an important research direction of the analog multiplier. Proposed analog multiplier using active attenuator significantly increases the input voltage range, more importantly, the introduction of negative feedback effectively reduces the nonlinear error of the multiplier in the active damping circuit. Based CSMC 0.5um BCD process, using Hspice for simulation, the conditions under 5V supply voltage, an input terminal of the multiplier input range is 0 ~ 2V, nonlinear error is less than 0.6%, the other input terminal range is 1 ~ 4V , nonlinear error is less than 0.3%.The total harmonic distortion is less than 1.8%.
【Key words】 Analogmultiplier; APFC; Voltageattenuation; High linearity;
- 【文献出处】 中国集成电路 ,China Integrated Circuit , 编辑部邮箱 ,2014年08期
- 【分类号】TP342.2
- 【被引频次】2
- 【下载频次】112