【摘要】 基于FPGA的时间间隔测量,由于其精度高、成本低、系统结构简单等突出优点,在时间间隔测量领域已成为主要研究方向之一。介绍了一种基于FPGA延迟链差值的时间间隔测量方法,利用片内单元缓冲器与触发器组成的延迟链形成的延迟链差值进行时间间隔测量,整个系统占用了较少的芯片资源。此方法既可为功能电路独立使用,也可通过FPGA中Logic Lock反标注进行系统的移植。此次研究建立在Altera公司的Cyclone系列二代芯片上,时序仿真表明时间间隔测量误差小于1ns,硬件测试精度优于2ns。更多还原

【Abstract】 A time-interval measurement method is described,which is based on chain delay difference of FPGA,using the delay chain consisting of the on-chip buffer unit and trigger doing time-interval measurement.The system takes up less chip resources.This method can be used independently as a function of the circuit,but also transplanted by anti-tagging using the FPGA logic lock.The study based on Altera’s Cyclone seriesⅡ chip,timing simulation shows that the time interval measurement error is less than 1ns,hardware testing accuracy is better than 2ns.更多还原