【摘要】 针对植入式医疗电子的应用需求设计了一个8位100 kS/s的低功耗逐次逼近型模数转换器(SAR ADC),并且基于0.13μm 1P8M工艺进行了流片(tape-out)验证.为了达到降低功耗的设计目标,对SAR ADC的子模块进行了仔细的分析设计:采用满足精度和速度要求的无源互补开关;采用失调(offset)优化的无静态电流的动态比较器;采用无静态功耗的电容阵列子数模转化器.测试结果表明,当输入测试信号为9.37 kHz时,该SAR ADC的信号噪声失真比(SNDR)为49.2 dB,动态无杂散范围(SFDR)为63 dB,有效位(ENOB)为7.8位.其微分非线性(DNL)和积分非线性(INL)分别为-0.15/+0.15 LSB和-0.35/+0.23 LSB,功耗为3.2μW,优值(FoM)为143 fJ/conversion-step.更多还原

【Abstract】 An 8-bit 100-kS/s successive approximation register(SAR) analog-to-digital convertor(ADC) is presented.Passive complementary NMOS and PMOS switches,a dynamic comparator and a binary-weighted capacitor DAC are adopted to preserve the desired low-power characteristic.According to the measured results,the SAR ADC has a signalto-noise distortion ratio(SNDR) of 49.2 dB,and the spurious free dynamic range(SFDR) of 63 dB for a 9.37 kHz fullscale input sinusoidal wave.The effective number of bit(ENOB) is 7.8 bits.The differential nonlinearity(DNL) is in the range of-0.15/+ 0.15 LSB whereas the integral nonlinearity(INL) is within-0.35/+ 0.23 LSB.The total power is 3.2 μW and the Figure of Merit(FoM) is 143 fJ/conversion-step.The SAR ADC is tape-out in standard 0.13μm 1P8 M process.更多还原