A 4 GHz CMOS multiplier for sigma–delta modulated signals

【摘要】 An integrated circuit design of a high speed multiplier for direct sigma–delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier’s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18- m CMOS process. The test results demonstrate thatthechiprealizesthemultiplicationfunctionandexhibitsanexcellentperformance.Itcanworkat4GHzandthe voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard.Additionally, the analysis of the multiplier’s noise performance is also presented.更多还原

【Abstract】 An integrated circuit design of a high speed multiplier for direct sigma–delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier’s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18- m CMOS process. The test results demonstrate thatthechiprealizesthemultiplicationfunctionandexhibitsanexcellentperformance.Itcanworkat4GHzandthe voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard.Additionally, the analysis of the multiplier’s noise performance is also presented.更多还原