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基于视频编解码的可重构处理器存储系统设计
Design of reconfigurable processor memory system for video codec
【摘要】 针对可重构视频编解码处理器ReMAP-2在高清视频编解码应用中对大规模数据吞吐率的需求,提出一种由全双工的帧缓存器及直接内存存取(direct memory access,DMA)组成的高速存储系统.其中帧缓存器由2个4 kbyte存储器构成,每个存储器分为16个存储块,采用二维地址编码,通过数据排列开关对像素数据的重排序,可满足视频编解码算法对子块像素数据快速读取的需求.仿真实验表明,该存储系统可满足可重构处理器ReMAP-2面向高清视频编解码的高性能处理应用需求
【Abstract】 A high-speed memory system is proposed for reconfigurable codec processor to access high data throughput rates in video codec applications.The full duplex frame buffer and direct memory access(DMA) are included in this new memory system.The frame buffer contains two memories with the size of 4 kbyte and is divided into 16 banks.Two-dimensional address coding is introduced as well as data arrangement switch for fast sequential data access by codec algorithm.The simulation result shows that the memory system can meet high performance requirement for reconfigurable processor ReMAP-2 in high-definition video codec application.
【Key words】 integrated circuit technology; reconfigurable; processor; digital signal processing; discrete cosine transform; memory; multimedia processing; video codec;
- 【文献出处】 深圳大学学报(理工版) ,Journal of Shenzhen University Science and Engineering , 编辑部邮箱 ,2013年02期
- 【分类号】TP333;TN919.81
- 【下载频次】96