节点文献
基于FPGA的PLC并行定时器的设计
Design of parallel timer in PLC based on FPGA
【摘要】 构建了一种采用ARM与FPGA协同并行工作实现定时功能的PLC控制系统。设计了ARM-FPGA系统的通信方式与协议,实现了ARM与FPGA之间快速高效的通信。由于PLC内部包含了数量较多的定时器,因此在FPGA中采用串行方式与并行方式相结合的方法实现PLC定时功能,经过分析与测试可知,该设计方法不仅可以保证定时器的计时误差在1ms以内,还能提高系统工作效率与减少硬件资源耗用。通过对FPGA内部功能模块的仿真测试与ARM-FPGA系统联合测试,验证了ARM-FPGA系统可以初步实现PLC的预期功能,其中FPGA可以稳定精确地实现定时功能。
【Abstract】 A PLC control system is built to achieve timing function,based on ARM and FPGA collaborative work in parallel.A communication mode and protocol of ARM-FPGA system is designed and a fast and efficient communication between the ARM and FPGA is achieved.The timing function of PLC in the FPGA combining serial mode and parallel mode is achieved,because of the PLC contains a large number of timers.The analysis and test show that the design method can not only ensure the timing error of timers within 1ms or less,but also improve system efficiency and reduce the consumption of hardware resource.The simulation testing of the functional modules of the internal FPGA and the joint tests of ARM-FPGA system verify that the desired functionality of the PLC is initially realized by the ARM-FPGA system,in which the FPGA can achieve stable and accurate timing function.
【Key words】 PLC; timing; FPGA; ARM; communication; timing error;
- 【文献出处】 计算机工程与设计 ,Computer Engineering and Design , 编辑部邮箱 ,2013年04期
- 【分类号】TP273
- 【被引频次】14
- 【下载频次】243