【摘要】 设计了一种用于分时长期演进(TD-LTE)系统基带信号处理的12bit40MS/s无校准的流水线模数转换器(ADC).在采样保持前端设计了一种改进的栅压自举开关,有效减少了电路的非线性失真,提高了开关的线性度.设计的ADC采用全2.5bit/级架构,利用级电路缩减技术满足面积与功耗要求.芯片基于130nmCMOS(互补金属氧化物半导体)工艺流片验证,电源电压1.2V.实测整个ADC,最大INL(积分非线性)和DNL(微分非线性)误差分别为1.48LSB(最低有效位)和0.48LSB.动态特性测试结果表明:在40MS/s采样频率、-1dBFS(满度相对电平)、4.3MHz正弦输入下,设计的模数转换器信噪失真比(SNDR)达到63.55dB,无杂散动态范围(SFDR)达到76.37dB.整个ADC在40MS/s全速工作时功耗48mW,芯片面积(包含Pad)为3.1mm×1.4mm.更多还原

【Abstract】 A 12 bit 40 MS/s calibration-free pipelined analog-to-digital convert (ADC) used in TD-LTE(time division long term evolution) baseband was described. A gate-bootstrapping switch′ s linearity was improved and designed as the input-sampling switches in the front sample-and-hold (S/H) circuit in order to reduce the nonlinearity distortion of the ADC effectively. To achieve low power and small chip size, the pipelined stages were scaled in current and area, and implemented with 2.5 bit/stage architecture. The ADC was fabricated in 130 nm CMOS(complementary metal oxide semiconductor) process with 1.2 V power supply. The results show that the ADC achieves 63.55 dB signal-to-noise and distortion ration (SNDR), 76.37 dB spurious free dynamic range (SFDR) under the conditions of 40 MS/s sampling rate and -1 dBFS (dB full scale), 4.3 MHz sinusoidal input signal. The measured maximum integral nonlinearities (INL) errors and differential nonlinearities (DNL) errors are 1.48 LSB (least significant bit) and 0.48 LSB at 12 bit level, respectively. The entire ADC consumes 48 mW when operating at 40 MS/s sampling rate and the chip size (including Pad)occupies 3.1 mm×1.4 mm.更多还原