【摘要】 本文给出一种利用DDR3高速存储芯片完成雷达数据重排的方法,详细描述了基于赛灵思FPGA的DDR3接口控制逻辑设计,并应用于工程实际提高了雷达信号处理的存储能力,满足新体制雷达大批量数据处理需求。更多还原

【Abstract】 A method of using DDR3 high speed memory chip to accomplish radar data rearrangement is presented;DDR3 interface control logic design based on Xinlinx FPGA is depicted in detail,which is applied in practical engineering so as to increase memory capability of radar signal processing,and meet mass-data processing requirement of new system radar.更多还原