【摘要】 本文设计了一款低功耗12-bit 50-MS/s逐次逼近型模数转换器,提出了一种动态比较器失调电压校正技术,取代了采用预放大器降低比较器失调电压的传统方法,解决了比较器低功耗和高精度之间的矛盾;基于时分复用的方法,改进了转换器核心数字逻辑,只需传统结构1/2的硬件电路便能实现相同的功能.此外,本文针对桥接电容和寄生电容引入的非线性问题做了详细的分析和公式推导.本设计采用SMIC 65nm标准CMOS工艺,核心芯片供电电压为1.2V,采样速率为50MS/s,版图后仿真结果表明,该ADC可达到71.5dB的信噪比和84.5dB的无杂散动态范围,功耗为4mW,芯片核心面积为0.3×0.2mm2.更多还原

【Abstract】 This paper presents a low-power 12-bit 50-MS/s successive approximation register analog-to-digital converter.A new calibration method is introduced to reduce dynamic comparator offset voltage.High power efficiency is achieved by eliminating pre-amplifiers.A novel digital control logic is employed based on time division multiple access.Compared to conventional logic,the number of logical gates is reduced by half.The effect of split capacitor and parasitic capacitance on the linearity of DAC are discussed in detail.The proposed ADC is implemented in SMIC 65 nm CMOS technology.The ADC achieves a peak SNDR of 72.7dB and a peak SFDR of 84.5dB at a 50-MS/s sampling rate.The core consumes 4mW with a 1.2-V supply,occupying an area of 0.06mm2.更多还原