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一种降低基带芯片功耗的时钟策略及改进方案

Clock Strategy and Its Enhancement for Reducing Baseband Chip’s Power Dissipation

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【作者】 程曾李同合马林何有志郑晓庆

【Author】 CHENG Zeng1,LI Tong-he1,MA Lin2,HE You-zhi1,ZHENG Xiao-qing3(1 Dept.of Microelectronics,School of Electronic and Information Engineering,Xi′an Jiaotong University, Xi′an 710049,China;2 School of Microelectronics,Xidian University,Xi′an 710071,China; 3 Key Laboratory of Physical Electronics and Devices of the Ministry of Education,School of Electronic and Information Engineering,Xi′an Jiaotong University,Xi′an 710049,China)

【机构】 西安交通大学电子与信息工程学院微电子学系西安电子科技大学微电子学院西安交通大学电子物理与器件教育部重点实验室电子与信息工程学院

【摘要】 为了更为有效地降低手机基带芯片中GSM通讯模块的功耗,将门控时钟策略和GSM通讯模块的特点结合起来,用硬件电路精确控制GSM通讯模块的休眠,并且对可能遇到提前唤醒的场景提出了改进方法,EDA软件仿真和FPGA验证了该方法可以达到明显的功耗优化效果.

【Abstract】 In order to reduce the power dissipation of GSM module of baseband chips more effectively,this paper combined clock gating and GSM module’s feature together,and controlled its power consumption precisely with hardware circuits;and enhancement method was proposed also for pre-wakeup situations.The results of EDA simulation and FPGA verification show that the proposed method can reduce the power dissipation obviously.

  • 【文献出处】 微电子学与计算机 ,Microelectronics & Computer , 编辑部邮箱 ,2012年02期
  • 【分类号】TN929.532;TN402
  • 【被引频次】4
  • 【下载频次】89
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