【摘要】 超宽带(UWB)通信系统需要高达480Mb/s的Viterbi译码器,而传统并行Viterbi译码器结构难以在现场可编程门阵列(field-programmable gate array,FPGA)上实现该速率。该文提出了独立前向滑块式并行Viterbi译码结构,解决了传统并行Viterbi译码器硬件实现存在的布线拥塞、逻辑资源消耗过大等技术难题,有效提高了系统最大工作时钟频率;同时,给出一种精简加比选单元(ACSU),通过减少加比选迭代运算阶数,降低了关键路径延时,进一步提高了系统最大工作时钟频率。完成4路并行Viterbi译码器的硬件设计,并在Xilinx Virtex-4FPGA上进行了验证,其最高译码速率达720Mb/s。更多还原

【Abstract】 Ultra-wideband(UWB) communication systems require Viterbi decoders with throughputs of up to 480 Mb/s,which cannot be accomplished in field-programmable gate array(FPGA) devices employing traditional parallel structures.A forward independent sliding-block structure was developed for Viterbi decoders to reduce the routing congestion and excessive consumption of logical resources in traditional structures,to achieve a higher maximum operating clock frequency.A simplified add-compare select unit(ACSU) using less iterations is used with a shorter critical path,which further increases the maximum operating clock frequency.A four-fold parallel Viterbi decoder has been implemented in a Xilinx Virtex-4 FPGA device with a maximum decoding rate of 720 Mb/s.更多还原