【摘要】 提出了一种针对专用、多通道、大电容负载LCD驱动芯片的测试方案。通过FPGA为待测样片提供12.5MHz的基本时钟、状态控制及帧频选择向量,并向数字部分寄存器写入递减数据,验证了芯片单路驱动200pF容性负载时可以实现1 024级灰度、12V摆幅输出。针对测试中出现的全摆幅上升时间较长及大输出幅度时的非线性问题,对芯片中的相关模块进行了测试分析,指出输出缓冲级对Miller电容的充电速度及数模转换器(DAC)对采样电容的充电速度是影响性能的关键因素,可通过适当减小片上转换电阻或采样电容来提高芯片性能。最后提出了一种使用开关电容型DAC及误差放大AB类输出驱动级电路的改进方案。更多还原

【Abstract】 This paper proposed a test scheme for a dedicated,multi-channel,large capacitor load LCD driver chip.The 12.5 MHz basic clock,control vectors for state change and frame frequency selection are provided by the FPGA,decreasing data is written to registers in the chip.With 200 pF capacitive load,the output signal range can realize 1 024 gray level and over 12 V voltage swing.Through testing the DAC and output buffer module in the chip,it is found that charging speed of the buffer to miller capacitor and the DAC to sampling capacitor cause the problem of longer full-swing rising/falling time and nonlinear output.It can be improved by reducing the on-chip convert resister or sampling capacitor to some extent.Finally,an improvement scheme is proposed,which uses switched-capacitor DAC and Class-AB output buffer error amplifier.更多还原