【摘要】 针对FPGA外部时钟信号过高的特点,在分析偶数分频和奇数分频的基础上,采用VHDL设计一种占空比为50%的数控分频器,并在QuartusⅡ环境下进行仿真实验。实验结果表明,设计方案是可行的,具有很强的实用价值。更多还原

【Abstract】 Aiming at the characteristic that FPGA external clock sign is too high,designs a numerical control frequency divider by using VHDL based on the analysis of even frequency division and odd frequency division.And simulates in Quartus II.The experimental result shows that the design of the frequency divider is feasible.更多还原