【摘要】 介绍一种基于四通道ADC的高速交错采样设计方法以及在FPGA平台上的实现。着重阐述四通道高速采样时钟的设计与实现、高速数据的同步接收以及采样数据的校正算法。实验及仿真结果表明,同步数据采集的结构设计和预处理算法,能良好抑制并行ADC输出信号因相位偏移、时钟抖动等造成的失配误差。更多还原

【Abstract】 The design method of a high-speed interleaved sampling system based on four-channel analog-to-digital converter(ADC) and its realization on Virtex-5 FPGA platform of Xilinx are introduced.The design of four-channel high-speed sampling clock,the synchronus receiving method of high-speed data and correction algorithm of sampling data are emphasized.Simulation results indicate that the structural design of the synchronus data sampling system and the pre-processing algorithm can suppress the mismatch error of parallel ADC output signal,which is caused by phase deviation and clock jittering.更多还原