【摘要】 为了降低数模混合片上系统(system on chip,SoC)的测试成本,基于片上虚数字化,提出了并行模拟测试外壳组设计,用数字自动测试设备和测试访问机制完成对各个模拟芯核的并行测试。在此基础上,建立了数模混合SoC测试调度优化问题模型,提出了一种基于递增生成的数模联合调度算法PADCOS,该算法具有复杂度低和优化效率高的优点。该文扩展并提出了用于验证数模混合SoC调度算法有效性的ITC 02m标准电路。实验在ITC 02m标准电路上采用PADCOS算法得到了数模混合SoC的优化调度方案,实验结果证明提出的并行测试外壳组相比于串行测试模式对测试时间的优化效果在30%以上。更多还原

【Abstract】 The tremendous testing cost of mixed-signal systems on chip(SoCs) can be reduced by a parallel wrapped analog core set designed using virtual digitization.The design provides parallel tests for multiple analog cores using digital automatic test equipments(ATEs) and a test access mechanism.Test scheduling optimization is used to develop an incremental parallel scheduling algorithm,PADCOS,which is a deterministic optimization algorithm with low time complexity and high optimization efficiency.An ITC’02m benchmark is extended to verify the efficiency of the test scheduling algorithm PADCOS for mixed-signal SoCs.The optimized test structure is more than 30% faster than a serial test structure.更多还原