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Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

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【作者】 刘慧敏张小兴戴宇杰吕英杰

【Author】 LIU Hui-min1,2, ZHANG Xiao-xing1, DAI Yu-jie1, and LV Ying-jie1 1. Institute of Microelectronics, Nankai University, Tianjin 300071, China 2. School of Electronics Information Engineering ,Tianjin University of Technology, Tianjin 300384, China

【机构】 Institute of Microelectronics,Nankai UniversitySchool of Electronics Information Engineering,Tianjin University of Technology

【摘要】 Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.

【Abstract】 Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.

  • 【文献出处】 Optoelectronics Letters ,光电子快报(英文版) , 编辑部邮箱 ,2011年05期
  • 【分类号】TN772
  • 【被引频次】3
  • 【下载频次】60
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