【摘要】 提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证。设计的Turbo并行高速解码器半次迭代的效率为6.9bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法。该设计节约了计算电路和存储量。更多还原

【Abstract】 Optimized implementation of a high speed parallel turbo decoder was proposed based on contention-free high-degree polynomial interleaver.The decoder,for which MAX-Log-MAP decoding algorithm was used,focused on QPP interleaver included in long term evolution(LTE) turbo code.The design was implemented with m language on Matlab,and verified with Verilog HDL.The parallel decoder was tested on LTE simulation system based on FPGA.The decoder achieved a 6.9 bit/cycle in half iteration and a throughput of 207 Mbit/s for 5.5 iterations and 309 MHz clock frequency,which satisfied requirements of high-speed B3G wireless system.For interleave and de-interleave,the method of memory mapping(MM) was adopted.Compared with conventional approaches,the proposed method could save memory resource and reduce interleave address computation units.更多还原