【摘要】 提出利用RTL数据通路中加法器、减法器、乘法器作为一种产生测试向量硬件的方法,对被测模块进行测试,以降低硬件开销。实验结果表明,该可测性设计与调度算法具备良好的性能和实用性。在满足功耗约束下,硬件开销可以降低10.7%~73.4%,同时测试应用时间也有所降低,最多可以降低22.4%。更多还原

【Abstract】 In order to reduce hardware overhead,this paper proposes a method where the adders,subtracters and multipliers inside of a data path are used to generate test vectors.Experimental results show that the proposed Design For Testability(DFT) and test scheduling approach has good performance and practicality.Under a given power constraint,the hardware overhead can be reduced from 10.7% to 73.4%.The test application time can also be reduced up to 22.4%.更多还原