【摘要】 设计了一个10 bit精度,50 MS/s采样频率的流水线型模数转换器,通过运算放大器共享和省略采样保持实现低功耗.第1级为单比特输出,它能够在将信号摆幅减半的同时保持信噪比不衰减,减半的摆幅使得运放直流增益和带宽要求以及电容匹配要求降低.由于采用运放共享技术,该设计只使用了4个运放,功耗相比传统结构降低1/3.采用0.35μm 2P4M CMOS工艺设计,在3.3 V电源电压下约消耗33 mW功耗,核心部分面积为2.2 mm2,采样频率50 MS/s,输入频率5 MHz时,SFDR为80.27 dB,THD为-77.45 dB,SNDR为61.17 dB.更多还原

【Abstract】 With SHA-less architecture and op amp-sharing technique,a low power 10bit 50MS/s pipelined analog-to-digital convertor(ADC) is proposed in this paper.The first stage with 1-bit-per-stage architecture achieves half signal swing while SNR still remains the same.The reduction of the signal swing allows relatively lower DC gain and bandwidth of op amp;it also relaxes the requirement of capacitor matching.Only four op amps are used in the design due to the opamp-sharing technique,resulting in more than 1/3 reduction on the power consumption.Implemented with 0.35μm 2P4M CMOS process,the ADC dissipates 33mW with a supply voltage of 3.3 V and occupies 2.2mm2 active area,the simulated SFDR is 80.27dB,THD is-77.45dB and SNDR is 61.17dB for input frequency of 5MHz at sampling rate of 50MS/s.更多还原