节点文献
铜互连氮化硅薄膜沉积技术中电压衰减的研究
BEOL Cu Interconnect SiN Deposition VBD Study
【摘要】 根据0.13μm以下的深亚微米超大规模集成电路中先进的后道铜互连技术对于氮化硅薄膜沉积的具体要求,文章在大马士革工艺的基础上分析了可能导致铜互连失效的原因。进而在应用材料公司的PRODUCER(一种薄膜沉积设备)机台上,通过包括对氨等离子体预处理和氮化硅预沉积的这两步骤作实验研究。利用田口分析判断的实验方法,找到主要影响电压衰减的因素,优化了气体流量、等离子喷头到晶圆表面的距离、射频功率、预处理和预沉积的时间等工艺参数。解决了0.13μm以下深亚微米中的铜互连的电压衰减问题,提高产品的良率和可靠性。
【Abstract】 Based on 0.13μm and beyond technology and advanced BEOL Cu interconnect process,the failure model which induced Cu interconnect failure was analyzed and the influence of "NH3 treatment" step and "Pre-Dep" step on VBD was focused in the paper.Based on Tagochi design analysis,the process parameters such as gas flow,heater spacing,RF power and time etc were optimized.The optimized process flow fixed VBD issue of BEOL completely,and enhanced production yield and reliability.In addition,the "SiH4 burst" issue,during Silicon nitride deposition,was prevented.
- 【文献出处】 电子与封装 ,Electronics & Packaging , 编辑部邮箱 ,2011年03期
- 【分类号】TN405
- 【被引频次】3
- 【下载频次】108