【摘要】 提高静态随机存储器(SRAM)的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅(SOI)基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61.8MeV/(mg/cm2),优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。更多还原

【Abstract】 Improving Single Event Upset(SEU) resistance of Static Random Access Memory(SRAM) is being a hotspot in the research area of electronics Radiation-Hardening.It is hard to improve the anti-SEU ability of bulk CMOS SRAMs without circuit Radiation-Hardening,whereas more area and power consumption will be spent with Radiation-Harding design.To investigate the SEU resistance of Silicon on Insulator(SOI) SRAMs,this study introduced the key technology breakthrough in SOI CMOS Radiation-Hardening process and 128 kb SRAM circuit design.The SEU experiment of a homemade 128 kb SOI SRAM showed that its threshold Linear Energy Transfer(LET) value was above 61.8 MeV/(mg/cm2),which was higher than that of CMOS SRAMs without Radiation-Hardening design.It is concluded that SOI fabrication process is promising to obtain preferable SEU resistance of SRAMs with proper considerations on basic device and 6-T cell structure.更多还原