【摘要】 随着集成电路特征尺寸进入纳米级,高能粒子造成的软错误已对电路的正常工作构成严重威胁。流水线电路具有工作频率高、时序单元数量多的特点,易受软错误影响。本文对时序单元进行容错性能分析,并结合流水线电路的特点,利用新型容错时序单元结构,提出了一种容软错误的流水线电路设计方案。更多还原

【Abstract】 As the feature sizes of integrate circuits decrease to nm,high-energy particles have posed a great threat to circuits’ normal function.Pipeline circuits that have high working frequency and a large number of sequential elements,are easily affected by soft error.This paper analyzes soft-error-tolerance on sequential elements.Based on pipeline circuits ’ character,a pipeline-circuit design method is proposed by using a new soft-error-tolerance latch structure.更多还原