【摘要】 设计了一个基于CSMC 0.5μm 2P3M CMOS工艺的Pipelined ADC.改进了末位量化的算法,通过对最低位的输出进行校正来消除误码,提高转换的精度.并优化设计了全电路的OTA模块,在增加一级单元的情况下,控制功耗为75 mW.在3.3 V电压供电的情况下,可以处理2V范围的输入电压,无杂散动态范围(SFDR)达到67.1 dB.更多还原

【Abstract】 A 10-bit 40-MS/s pipelined analog-to-digit converter which implemented in CSMC 0.5 μm 2P3M CMOS process is described.The converter have a offset calibration circuit for the lowest bit. This arithmetic can reduce the offset and improve the resolution.The OTAs used in the converter have been calculated, so the power of circuit is only 75 mW from a 3.3 V supply.The input voltage range is 2 V, and the spurious-free-dynamic-range(SFDR) is 67.1 dB.更多还原