【摘要】 设计了一种用于Pipelined ADCs中的前置采样保持电路。从理论上推导了12bit、100MHz的模数转换器对采样保持电路各个子电路的性能指标要求,按此要求设计了增益增强型运放、自举开关等子电路。基于SMIC0.13μm,3.3V工艺,Spectre仿真结果表明,在采样频率为100MS/s,输入信号频率为9.7656M时实现了81.9dB的信噪失真比(SINAD)和13.3位的有效位数(ENOB),无杂散动态范围(SFDR)可达94.9dB,功耗仅为24mW。输入直到奈奎斯特频率,仍能保持81.5dB的信噪失真比和13.2位的有效位数,SFDR可达到92.67dB。更多还原

【Abstract】 A sample and hold circuit used in the front end of Pipelined ADCs is designed. The performance index of all the sub-circuit are analyzed from the requirement of 12 bit,100MHz Analog-to-Digital Converters theoretically, and then the sub-circuit such as gain-boosted OTA、bootstrap switch is designed according to the above requirements. Base on SMIC 0.13μm, 3.3V technique, Spectre simulation shows that SINAD, SFDR and ENOB can reach 81.9dB, 94.9dB, and 13.3bit respectively,with only 24mw power consumption. Even the input signal is up to Nyquist frequency, its SINAD and SFDR can still keep 81.5dB and 92.67dB along with the 13.2bit ENOB.更多还原