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锁相式频率合成器的设计与改进

Design and Improvement of a Frequency Synthesizer Based on Phase-locked Loop

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【作者】 马宇飞李署坚

【Author】 MA Yu-fei,LI Shu-jian(College of Information and Electrical Engineering,Beijing University of Aeronautics and Astronautics,Beijing 100191,China)

【机构】 北京航空航天大学电子信息工程学院

【摘要】 针对目前的锁相式频率合成器分辨能力不高和频率转换时间较长的问题,采用DDS/PLL组合式频率合成器,信号频率的转换时间最短可达到80 ns;在输出前端采用增益可控放大电路,有效解决了信号输出强度随着频率升高而不断衰减的问题,使输出信号幅度稳定在1~1.05 V之间。详细论述了系统的总体结构、软硬件结构,并给出了实验测试结果。

【Abstract】 In allusion to the problem of weak discernibility and long conversion time of phase-locked loop(PLL) frequency synthesizer,the DDS/PLL combined frequency synthesizer is used,and the frequency coversion time is as short as 80ns.By using gain-controllable amplifier circuit in output port,the problem that the intensity of signal will be decaying with the increasing of frequency can be solved effectively,and the signal amplitude can stay 1~1.05 V.The system structure,hardware and software composition are detailed.The experimental results are also given.

  • 【文献出处】 电讯技术 ,Telecommunication Engineering , 编辑部邮箱 ,2010年07期
  • 【分类号】TN742.2
  • 【被引频次】12
  • 【下载频次】239
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