A novel wideband low phase noise 2:1 frequency divider

【摘要】 <正>This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm~2 of the core die area.更多还原

【Abstract】 This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm~2 of the core die area.更多还原