【摘要】 介绍了传统的数字锁相环提取位同步信号的原理,提出了一种改进的可变性能位同步电路FPGA实现方法,该方法首先通过相位比较器得到接收码元序列与本地位同步信号之间的相位差,根据相位差来控制K计数器的计数,由计数器去控制减加脉冲数。通过设置计数器的K值,可改变电路的最大相位误差及同步建立时间等性能。更多还原

【Abstract】 This paper introduces the principle of traditional digital phase—locked loop.An improved method of bit synchronization with changeable performance based on FPGA is presented.Phase difference between the local synchronization signal and the received symbols is got by phase comparator.Using the phase difference controls the counter.The counter controls the number of adding or deleting pulses in the corresponding gate.The max phase error and synchronization build time can be changed through the setting of different K.更多还原