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低功耗无片外电容的低压差线性稳压器

Low dropout linear regulator with no off-chip capacitor and low power consumption

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【作者】 崔传荣巩文超王忆何乐年

【Author】 CUI Chuan-rong,GONG Wen-chao,WANG Yi,HE Le-nian(Institute of VLSI Design,Zhejiang University,Hangzhou 310027,China)

【机构】 浙江大学超大规模集成电路研究所

【摘要】 设计了输出电压为3.3 V,最大输出电流为100 mA的无片外电容低压差线性稳压器(LDO).该芯片采用并行结构的微分器和大米勒电容,通过比例调节和微分调节结合的方式,利用微分器电路在瞬间提供大的转换电流,克服了无片外电容LDO在负载和电源电压变化时输出电压跳变过大的问题.芯片采用CSMC公司0.5μm工艺模型设计,并经过流片.测试结果表明,在5 V工作电压下,当负载电流从100 mA在1μs内下降到1 mA时,输出电压变化小于600 mV;电路的静态电流小于4.5μA.测试结果验证了电路设计的正确性.

【Abstract】 A low dropout linear regulator(LDO) with no off-chip capacitor and maximal output current of 100 mA and 3.3 V output voltage was designed and implemented by using CSMC’s 0.5 μm mixed-signal technology.By using a parallel structure constituted by differentiator,Miller capacitor and error amplifier,the circuit can supply a large current for state conversion in a moment.Therefore,when the load current or supply voltage changes,the varieties of transient output voltage are acceptable under the condition of no off-chip capacitor.The chip testing results revealed that under the supply voltage of 5 V,as the load current decreased from 100 mA to 1 mA within 1 μs,the ripple of output voltage was less than 600 mV;and the quiescent current was measured to be less than 4.5 μA.The designed circuit was validated by the results of the chip test.

【基金】 浙江省重点科技计划资助项目(2007C2102)
  • 【文献出处】 浙江大学学报(工学版) ,Journal of Zhejiang University(Engineering Science) , 编辑部邮箱 ,2009年11期
  • 【分类号】TM44
  • 【被引频次】9
  • 【下载频次】312
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