【摘要】 提出一种8bit、1GHz采样率的电流导引的一元控制型温度译码D/A转换IP核的设计。分段的行、列温度译码器提高了选通电流源单元的精确性;二次锁存器的应用有效地降低系统对时钟的抖动,减小功耗。重点分析关键电路的设计,并基于Cadence 2.5V电压、TSMC 0.25μm CMOS工艺进行仿真验证。测试结果表明,D/A转换有效数据为7.2bit,单音主杂比52.5dB,积分非线性误差和微分非线性误差分别为±0.35LSB和±0.38LSB,D/A转换的版图面积为1.00mm×1.25mm,符合遥测系统中SOC的嵌入式设计要求。更多还原

【Abstract】 An IP core design of 8bit,1GHz sample-rate current-guided unary controlled module thermometer-decoded D/A converter is presented.Segmented row,column thermometer-decoders improve the accuracy of selected current-source units.Applications of two-class laches reduce the system’s clock jitter effectively and lower the power.This paper focuses on the design of several key circuits.Simulation and test are carried out based on the Cadence 2.5V voltage and TSMC 0.25μm CMOS technique.Results show that the ENOB of D/A converter is 7.2 bit,the SFDR is 52.5dB,the INL and DNL are respectively ±0.35LSB and ±0.38LSB,and the layout area of D/A converter is 1.00mm×1.25mm.The D/A converter is suitable for the SOC embedded application in telemetry systems.更多还原