【摘要】 设计一种新型准并行LDPC分层译码器,实现对0.5码率,4608码长(3,6)规则准循环LDPC的实时译码.并在Altera公司的Stratix Ⅱ系列EP2S60器件上完成了布局布线.最高工作频94.47MHz,当最大迭代次数为25次时译码吞吐量可达58.70Mbps.与传统的TPMP译码方案相比,可减少近一半的平均译码迭代次数,而且可以显著降低RAM块的使用数量.整个设计具有很强的扩展性和通用性,只需作事先存储校验矩阵式样及行重信息,即可支持任意码率、规则及非规则码的准循环LDPC译码.更多还原

【Abstract】 A novel quasi-parallel layered LDPC decoder was presented,which can complete real-time decoding for 1/2 code rate,(3,6) regular QC-LDPC code with 4608-bit code length.Whole design was synthesized under Stratix II EP2S60 FPGA of Altera,Inc.Highest clock frequency after routed reaches 94.47 MHz,when maximum iterative No.is set to 25,corresponding decoder throughputs come to over 58 Mbps.Compared with traditional TPMP decoding strategy,average iterative No.were decreased nearly by half,consumed RAM block No.were reduced greatly,too.With LDPC parity-check matrix pattern plus row-weight information recorded,this LDPC decoder also can support any code lengths and code rates for arbitrary QC-LDPC codes.更多还原