【摘要】 根据一种时间数字转换器的结构和性能,提出了组成全数字锁相环重要模块——时间数字转换器的设计方法。首先,设计出TDC模块的电路构成;其次,采用千分尺算法对电路信号进行设计和较正;最后,通过PSPICE仿真环境对电路图的设计,测出TDC的精确度,测得在CMOS环境下时间延迟的线性趋势。实验结果表明,与已有的时间数字转换器相比,该千分尺算法应用于TDC模块的设计,可以使时间数字转换器的性能有较大提高。更多还原

【Abstract】 According to a time digital converter on the structure and performance,design an important component of DPLL module-time digital converter.First,design the circuit TDC module;Second,the Self-correct algorithm used to signal circuit design;Finally,PSPICE simulation environment for circuit design,measured the precision of the TDC,measured in time delay CMOS environment The linear trend.The results show that,and the time has been compared to digital converters,the 1,000-foot algorithm used in the design of TDC module can be time-digital converter,so that the performance has improved greatly.更多还原