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双阈值VLSI低测试功耗方法研究
Research on novel low test power based on two threshold VLSI
【摘要】 提出一种测试功耗优化的新方法,它通过阈值门电路调节和漏电流优化两种方法相结合来降低静态功耗。通过算法寻找电路的关键路径,去除伪路径,然后在关键电路上设置低阈值门电路,在非关键电路上设置高阈值门电路(不违反时序约束的前提下),利用测试向量的无关位特性来调整测试向量和测试架构,达到降低漏电流的目的。通过以上两种途径,整体上达到功耗优化的结果,实验结果证实了本方法的有效性。
【Abstract】 This paper proposed a new test power consumption optimization approach,it reduced the static power consuming through voltage scaling and leakage optimization.To find the critical path through the algorithm,eliminate the false path,and then set low threshold voltage on the critical path,set high threshold voltage on the non-critical paths(without violating the timing constraints).To regular the test vector and modify the test architecture based on the don’t care bits,so it could reduce the leakage current.With the two ways,got a better optimization result.The experiment shows the efficiency.
【Key words】 test power consuming; voltage scaling; leakage current optimization; test vector;
- 【文献出处】 计算机应用研究 ,Application Research of Computers , 编辑部邮箱 ,2009年04期
- 【分类号】TN47
- 【被引频次】4
- 【下载频次】64