【摘要】 提出了一种用于Σ-Δ DAC(增量总和数模转换器)的插值滤波器设计,可对不同采样率的PCM数据实现8倍插值。该滤波器对流水线结构进行优化,提高了计算速度,并可根据不同的采样率自适应地调整时钟频率,以降低电路的动态功耗。滤波器电路由Verilog HDL语言实现,经逻辑综合与仿真,表明其功能正确且具有面积小,功耗低的优点。更多还原

【Abstract】 In this paper,an optimized interpolation filter used in ΣΔ DAC is presented.This filter accomplishes the function of timing a different sample rate of PCM code by 8.The newly designed pipeline structure in this filter obviously improves the executive speed,while in addition,the system clock for the interpolation module is also adjustable referring to the sample rate in order to reduce the power consumption efficiently.The whole filter realization is implemented with Verilog HDL and the synthesization results after correct simulation shows that this interpolation filter has the advantage of a small on chip area and low power consumption.更多还原