【摘要】 针对最新的视频压缩标准H.264/AVC,提出一种并行化的CAVLC编码器架构。该编码器并行化处理CAVLC中的语法元素,可减少编码量化后的变换系数的时钟周期。通过在Altera的Quartus Ⅱ FPGA开发软件下的试验表明,该编码器能够实时编码1920×108030fps格式的视频。更多还原

【Abstract】 This paper presents a parallel architecture of CAVLC encoder in the new H.264/AVC video compression standard.To decrease the encoding cycles,the proposed design encodes the syntax elements in CAVLC using a parallel architecture. After synthesis in Quartus Ⅱ FPGA development software,the result shows that the proposed design is capable of real-time processing for 1920x1080 30fpgs videos.更多还原