【摘要】 对高频率数据总线运行下的移动终端PCB设计进行了论述。为了便于分析,引入了时序系统机理介绍。同时对高性能移动终端PCB设计中最重要和必需的布线设计部分进行了深入的关注。结合延迟控制技术对数据总线优化公式中的延迟预测和噪声裕量做了一定的讨论。最后,通过常用器件参数得到商业可用的DDR SDRAM设计参考并使用HyperLynx进行了眼图模板仿真验证。更多还原

【Abstract】 This paper describes the design of mobile terminal printed circuit board(PCB),when its data bus is in high frequency performance.For the analysis,the timing system mechanism was introduced.Also,the layout designing in high performance mobile terminal PCB design is focused as the most important and necessary part.The delay skew budget and noise margin allocation for the data bus of the optimization equations are discussed in conjunction with their associated delay skew control techniques.Finally,design guidelines are given for commercially available double data rate(DDR)synchronous dynamic random access memory(SDRAM)designs using parameter of usual component and simulated with eye diagram model by HyperLynx.更多还原