【摘要】 低密度奇偶校验码(LDPC码)以其接近香浓极限的性能得到了广泛的应用。如何在FPGA上实现多码率LDPC码的高速译码,则是LDPC码应用的一个焦点。本文介绍了一种多码率LDPC码及其简化的和积译码算法;设计了这种多码率LDPC码的高速译码器,该译码器拥有半并行的运算结构和不同码率码共用相同的存储单元的存储资源利用结构,并以和算法与积算法功能单元同时工作的机制交替完成对两个码字的译码,提高了资源利用率和译码速率。最后,本文采用该结构在FPGA平台上实现了码长8064比特码率7/8、6/8、5/8、4/8、3/8五个码率的多码率LDPC码译码器。测试结果表明,译码器的有效符号速率达到200Mbps。更多还原

【Abstract】 With near Shannon capability,low-density parity-check(LDPC) codes have initiated wide scale interests in wireless telecommunication fields.Recently how to implement decoders for multi-rate LDPC code attract much attention.In this paper,a class of multi-rate LDPC codes and its simplified decoding algorithms are presented.Based on semi-parallel and storage resource reusing architecture,a decoder for multi-rate LDPC code is designed to decode two LDPC codes at the same time.This decoder has been implemented on a FPGA platform and can work for 8064 bit code length at rate 7/8,6/8,5/8,4/8 and 3/8.Test results show that its code throughput can approach 200 Mbps.更多还原