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基于FPGA的RS编码器设计与实现

Design and Realization of RS Encoder Based on FPGA

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【作者】 张怡崔永军杨晓亚毛得明

【Author】 ZHANG Yi1,CUI Yongjun1,YANG Xiaoya2,MAO Deming1(1 School of Electronics and Information,Northwestern Polytechnical University,Xi’an 710129,China;2 Xi’an Military Academy,Xi’an 710108,China)

【机构】 西北工业大学电子信息学院西安陆军学院

【摘要】 通过对通信系统中RS编码器的分析和研究,发现传统的RS编码器存在电路结构复杂,处理速度慢的问题。文中采用了一种新的编码器构造方法,利用生成多项式系数的对称性,在Quartus7.0编译环境下设计了对称结构的RS(255,223)编码器,且使用ModelSim与Matlab相结合的方法对编码器进行调试、仿真、验证。仿真结果表明:编码器性能良好,与已有的该项设计相比,具有速度快和占用硬件资源少的特点。

【Abstract】 By analyzing and researching the RS encoder in communication system,it is found the problems of complex circuit structure and low processing speed occurred to traditional RS encoder.Focused on the problems,a new encoder construction method was proposed.A RS(255,223) encoder with symmetric coefficients of generator polynomial was implemented under the Quartus7.0,and test,simulation and validation were conducted under Matlab and ModelSim.The simulation result indicates that the performance of the encoder is better,and the encoder is featured with high speed and low hardware complexity.

  • 【文献出处】 弹箭与制导学报 ,Journal of Projectiles,Rockets,Missiles and Guidance , 编辑部邮箱 ,2009年05期
  • 【分类号】TN762
  • 【被引频次】7
  • 【下载频次】189
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