【摘要】 随着混沌理论应用于产生伪随机序列的发展,用现场可编程逻辑门阵列实现了基于TD-ERCS混沌的伪随机序列发生器.为了便于硬件实现并减少硬件占用资源,对原算法(即基于TD-ERCS构造伪随机序列发生器的算法)进行了适当改进,密钥空间缩减到2160.设计采用双精度浮点运算,选用Cy-clone系列的EP1C20F400芯片,完成了CPRSG的系统仿真实验.系统的硬件电路占用17716个逻辑单元,占芯片资源88%,工作频率50 MHz,CPRS产生速率10 Mbps.更多还原

【Abstract】 With the development of chaos theory based pseudo-random number generator(PRNG),in this paper,a FPGA(Field Programmable Gate Array) based implementations of a chaotic pseudo-random sequence generator(CPRSG) is presented.It is a bit serial implementation of a pseudo-random number generator based on TD-ERCS which is appropriately improved and the key space of CPRSG is reduced to 2160 in order to facilitate the realization of hardware and reduce hardware resources occupied.An effort of synthesizing the improved algorithm into a Cyclone EP1C20F400 FPGA is also reported.The design is with double-precision floating-point operations and the system hardware circuit occupies 17,716 logical elements,accounting for 88% chip resources.Elementary hardware simulation results show that the throughput of the CPRSG chip reaches up to 10 Mbps under a running condition of 50 MHz clock frequency.更多还原