【摘要】 在分析RS解码算法的基础上,使用便于VLSI实现和流水线设计的矢量运算对该算法进行了全新的剖析和推演,并依据所采用矢量法则的运算特征提出一种面积优化的RS解码器体系结构.通过流水线、部件复用、折叠以及共享电路等设计,该体系结构大大提高了解码器主要运算部件的复用率,降低了电路复杂度,删减了冗余电路,缩减了电路规模.基于该体系结构设计的RS(204,188)解码器规模约为27,000门,与同类设计相比电路规模可降低39%,其已集成到一款HDTV信道调制解调芯片中并在实际中得到应用.更多还原

【Abstract】 In this paper,the known decoding procedure for Reed-Solomon(RS)code is analyzed in the way of vector operations that are suitable for VLSI implementation and pipelining.Then,a new area-efficient architecture for RS decoder is proposed.By pipelining,reusing computation unit,folding and sharing circuit,the proposed architecture can improve the reuse rate of the main computation unit for the decoder,decrease the hardware complexity,delete the redundancy circuit and reduce the circuit area.The results show that the total number of gates of the proposed RS(204,188)decoder is about 27,000 gates,which is about 39% smaller than the same kind of conventional ones.It has been integrated in a channel demodulation chip for HDTV and the chip has been tested successfully in practice.更多还原