【摘要】 本文在设计实现乘法器时,采用了4-2和5-2混合压缩器对部分积进行压缩,减少了乘法器的延时和资源占用率;经Xilinx ISE和QuartusⅡ两种集成开发环境下的综合仿真测试,与用Verilog HDL语言实现的两位阵列乘法器和传统的Booth编码乘法器进行了性能比较,得出用这种混合压缩的器乘法器要比传统的4-2压缩器构成的乘法器速度提高了10%,硬件资源占用减少了1%。更多还原

【Abstract】 Using 4-2 compressor and 5-2 compressor to compress partial products, while designing multiplier to reduce the delay of time and ratio of resource. Comparing performance of multiplier described in Verilog HDL on speed、area and the utilization ratio of resource in the integrated exploitation environment of Xilinx ISE and Quartus II. the speed of this multiplier is increased by 10% and its hardware resource is reduced by 1%.更多还原