【摘要】 本文首先介绍了CORDIC算法原理和IEEE-754标准化结构,然后在传统CORDIC算法的基础之上,用Verilog HDL语言对CORDIC内核及前后处理单元进行了编程与设计,通过增加迭代次数,对参数进行了优化筛选,提高了运算精度,使设计出的软核能够在精度要求较高的场合中运行,输出数据经过IEEE-754标准化处理,能够直接兼容大多数处理器,扩展了其应用范围。最后在Quartus Ⅱ 5.1上进行了时序仿真,设计结果表明该算法在硬件上具有很大的优势。更多还原

【Abstract】 First,this paper introduces the principle of CORDIC algorithm and the structure of standarded IEEE-754. Based on the traditional CORDIC algorithm,programs and design the CORDIC kernel cores and processor unit with Verilog HDL language. It im-proves the calculation precision through increasing the iteration times,optimizing and selecting the arguments,making the designed soft-core adapted to higher precision required occasion. The output data can be directly compatible with most of the processors by the IEEE-754 standard processing,so its application area is widely extended. Finally it carries out the timing simulation with Quar-tus Ⅱ 5.1,the result shows that the algorithm has a great edge in the hardware.更多还原