【摘要】 介绍了一种适用于10位80MS/s流水线模数转换器(Pipelined ADC)的采样/保持(S/H)电路。该电路为开关电容结构,以0.25μm CMOS工艺实现。采用栅源电压恒定的栅压自举开关和底极板采样技术,极大地减小了采样的非线性失真。基于该S/H电路的流水线A/D转换器在80MHz采样率下,输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为84.9dB,有效位数(ENOB)达到10位。更多还原

【Abstract】 In this paper,a sample and hold circuit for a 10bit 80MS/s pipelined A/D converter has been designed,which is implemented in a TSMC 0.25μm CMOS process.The S/H circuit is realized in switched-capacitor topology.Using switch gate voltage bootstrapping for constant Vgs and bottom plate sampling techniques,nonlinear distortion is reduced significantly.The A/D converter based on this S/H circuit achieves a SFDR of 84.9dB at 80MHz sampling rate.更多还原