【摘要】 为了解决数字VLSI实现BP网络时会引起矩阵转置和处理器内部数据通信的问题,提高可编程处理器的并行度,本文从硬件实现的角度,基于BP网络的算法特点,对这两个问题进行分析,设计了一种适于BP网络的并行度较高的可编程数字处理器的体系结构。该处理器基于分布式存储的SIMD结构,采用一维脉动阵列实现矩阵转置以及全联通的数据通路实现处理器的内部数据通信,减小这两方面引起的开销。该处理器在FPGA上进行了功能仿真,时钟频率为45MHz,与PC机、DSP、专用芯片等进行比较,实验结果表明BP网络在该处理器上运行可以达到较高的速度。更多还原

【Abstract】 To resolve the main problems of the digital VLSI for realizing the BP neural network: matrix transpose and the data communication inside the processor,and to enhance the parallelism of the processor,two problems for the hardware realization based on the BP algorithm are analyzed and a parallel programmable architecture for realizing BP neural network with a higher parallelism is designed.The processor has single instruction stream multiple data stream(SIMD) architecture with distributed memory,uses the one-dimensional systolic for the matrix transpose and the full connection for the inner communication,thus reducing the time spending.The processor is simulated on FPGA in 45 MHz.Compared with PC,DSP and the custom chip,experimental data show that BP neural network can run fast in the processor.更多还原