节点文献
Chip Multithreaded Consistency Model
【摘要】 <正>Multithreaded technique is the developing trend of high performance processor.Memory consistency model is essential to the correctness,performance and complexity of multithreaded processor.The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper.The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized.With the idea of critical cycle built by Wei-Wu Hu,we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model.Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and ensures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor.The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed.Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.
【Abstract】 Multithreaded technique is the developing trend of high performance processor.Memory consistency model is essential to the correctness,performance and complexity of multithreaded processor.The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper.The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized.With the idea of critical cycle built by Wei-Wu Hu,we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model.Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and ensures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor.The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed.Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.
【Key words】 computer architecture; Godson-2; multithreading; memory consistency model; event ordering;
- 【文献出处】 Journal of Computer Science & Technology ,计算机科学技术学报(英文版) , 编辑部邮箱 ,2008年02期
- 【分类号】TN402
- 【被引频次】1
- 【下载频次】52