【摘要】 在多FPGA设计中,时钟信号的传输延时造成了FPGA间的大时钟偏差,进而制约系统性能。为减少时钟偏差,该文提出一种多数字延迟锁相环(DLL)电路。该电路将时钟的传输电路放入DLL的反馈环路。利用DLL的延迟锁定特性,对FPGA间的时钟传输延时进行补偿,减少FPGA间的时钟偏差,解决多FPGA的时钟同步问题。更多还原

【Abstract】 In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance. To decrease this skew, a circuit based on Delayed Locked Loop(DLL) circuits is proposed. This circuit links the clock transfer path into the feedback loop of DLLs. Thanks to the delayed locked feature, the delay of clock transfer is compensated. Therefore, this circuit reduces the skew between FPGAs and solves the synchronization in multi-FPGA designs.更多还原