【摘要】 提出了实现r-port电路的set-C单元的两种不同实现方案set-C1与set-C2,给出了r-port电路及set-C1与set-C2的管级电路图,并分析了它们的工作原理。基于0.25μm标准CMOS无比(ratioless)工艺,给出了r-port电路的仿真图及set-C1与set-C2在上升延迟与平均功耗特性方面的HSPICE对比曲线。仿真结果表明,set-C1、set-C2的最小上升延迟分别为0.154ns和0.244ns,比值为1:1.58;set-C1较set-C2节省的最大功耗可达31%。由此得出set-C1较佳的结论。更多还原

【Abstract】 Two designs of set-C element for implementation of r-port circuit are introduced,they are named set-C1 and set-C2.Also,the circuit models of transistor level and the working principles of each design and r-port circuit are presented.The simulation figure of r-port circuit,curves of rising delay and average power of the two designs by HSPICE simulation are showed based on typical 0.25 μm CMOS ratioless technology.Simulation result reveals that the lowest rising delay of set-C1 and set-C2 is 0.154 ns and 0.244 ns respectively,with the ratio of 1:1.58.Set-C1 would be saving as much as about 31% in power over set-C2.It is showed that in a typical environment,set-C1 is superior to set-C2.更多还原