【摘要】 在MATLAB/Simulink的平台上,设计并实现了一种新的10bit Pipeline ADC的系统仿真模型。针对2bit,共9级的结构的精度不足以及4bit首级结构的功耗较大的特点,提出了一种首级3bit,共8级的结构。这种结构可以实现精度和功耗的平衡。经过系统仿真,在输入信号为10MHz,采样时钟频率为40MHz时,系统最大的SNR=60.6dB,SFDR=82.177dB。创建的系统模型可为ADC系统中的误差和静态特性研究提供借鉴。更多还原

【Abstract】 A novel pipeline ADC structure based on MATLAB/Simulink toolbox is proposed.In order to balance higher power dissipation in 4 bit first-stage architecture and lower precision in 2 bit per-stage structure,a 8-stage type with 3 bit first stage is introduced. Simulation results indicate that the maximum SNR(Signal to Noise Ratio) and SFDR(Spurious Free Dynamic Range) of this ADC(Analog to Digital Conversion) are 60.6 dB and 82.177 dB respectively, with the input signal frequency of 10 MHz and sampling clock of 40 MHz. The model of novel pipeline ADC can give helpful information on improving system error performance and research on system static characteristic.更多还原