【摘要】 信号源是电子系统中重要的组成部分。随着电子技术的不断发展,对信号源的要求越来越高,传统的模拟信号源已经远远不能满足要求,而直接数字合成技术的出现,给现代电子技术带来了新的生机。文章在分析了DDS原理、CORDIC算法原理的基础上,提出了一种基于CORDIC算法的全流水线型DDS结构。使用verilogHDL编写了RTL级代码,并进行了综合、布局布线、后仿真验证等。工作频率为176.65MHz,输入频率控制字为48位,输出幅度为16位,频率分辨率为6.27×10-7Hz。更多还原

【Abstract】 The signal source is an important part in the electronic system. Along with continuous development of the electronic technical, the request of the signal source is more and more high and the traditional simulant signal source cound’t satisfy the request any more. The emergence of direct digital frequency synthesis has brought much vitality for modern electronic science and technology.This paper presents a full pipelining DDS architecture based on principle of DDS and CORDIC algorithm. Encoding with verilog HDL and synthesis, placement and routing,simulation ect..Frequency is 176.65MHz.The input frequency control word is 48 bit,the output amplitude is 16 bit,the frequency resolution is 6.27×10-7Hz.更多还原