【摘要】 文章实现了一种应用于串行通信中的抗噪声接收电路的设计。UART被广泛应用于在远端设备之间进行串行通信,传统接收电路在位周期的中央对信号进行采样,但是由于各种随机噪声的干扰,会引起数据采样错误,造成通信出错。文章提出的设计方法是利用一个累加器在一个特定窗口周期内对串行数据进行采样并累加,再根据累加和判断出窗口期内正确数据位,从而滤去串行线路上的噪声得到纯净的串行数据,这大大增强了串行通信的可靠性。文章利用Quartus软件对设计进行编译、综合、仿真。仿真结果表明该电路能有效滤去串行线路上噪声,极大增强了接收电路的抗噪声性能。更多还原

【Abstract】 This paper designs an anti-noisy UART receiver circuit which used in serial communication. UART is used to implement serial communication between two remote devices, in classical circuits, the receiver samples the data in the center of the bit period, because of the various random noisy interference, the receiver may sample the wrong data, so the corresponding faults occurs. This design utilizes an accumulator samples and accumu-lates the serial data between a so called window period, then produces the right data according of the accumu-lative sum, it improves the serial communication performance greatly. Quartus software is used to complete the design process, including compilation, synthesis and simulation. The simulation result indicates that the design can remove the noise from the serial line efficiently, enhance the anti-noisy performance of UART receiver enormously.更多还原